ICI, OCS, slices and pods

Tick each objective you can deliver out loud without notes. Then write the one-paragraph explanation you would give a room of GPU engineers. Saved attempts stay below, so you can compare them over the week.

• I can describe the TPU topologies — a 2D torus on v5e and v6e, OCS-joined 4×4×4 cubes forming a 3D torus on v4, v5p and Ironwood, and Boardfly on 8i — and say which slice shapes have wraparound.
• I can convert a Cloud-docs ICI figure (per chip, both directions, all links) into per-link one-way bandwidth and into the per-axis bandwidth used in collective cost formulas.
• I can explain what optical circuit switches buy (reconfiguration, failure isolation, non-contiguous and twisted slices) and what they cost.
• I can rank HBM, ICI, PCIe and DCN for Ironwood with numbers, and say which parallelism belongs on each.
• I can compute hop counts, diameter and point-to-point transfer time on a slice, and say when a transfer is latency-bound rather than bandwidth-bound.
• I can explain why TPU 8i abandons the torus for Boardfly, using hop latency and decode traffic.
• I can compare TPU scale-up with NVLink domains and InfiniBand fat trees, and with Trainium's move from torus to switch.

Prompts to answer out loud

1. NVLink gives every GPU in an NVL72 rack one hop to the other 71. An Ironwood chip has 6 neighbours and the pod has 9,216 chips. Argue for each design with numbers.
2. Why do you get roughly half the collective bandwidth on a 2×2×2 slice compared with a 4×4×4 cube?
3. What did Google change in TPU 8i's network, and why, given what decode traffic looks like?
4. Walk the bandwidth ladder for Ironwood from HBM to DCN and say which kind of parallelism belongs at each rung.