Pallas, XProf and a design review

Tick each objective you can deliver out loud without notes. Then write the one-paragraph explanation you would give a room of GPU engineers. Saved attempts stay below, so you can compare them over the week.

• I can write and explain a Pallas TPU kernel — grid, BlockSpec index maps, the (8,128) rule, memory spaces, implicit double buffering, dimension_semantics and scratch accumulators — and say how it reaches the hardware through Mosaic.
• I can choose a Pallas tile size from arithmetic intensity and the VMEM budget.
• I can say when a Pallas kernel is worth writing on TPU and when XLA already does the job.
• I can capture a TPU profile from JAX and from tpu-inference, and read the Trace Viewer, including async -start/-done pairs.
• I can decode an HLO op line — shape, layout, tiling, memory space, fusion kind, called computation and replica groups.
• I can find a communication-overlap failure and a sharding mistake in a profile, and use the op profile and roofline tools to choose what to fix.
• I can run a design review — model, chip, SLO, mesh, quantization, batch, expected step time — and state the bottleneck in one sentence.

Prompts to answer out loud

1. Show me in this trace where communication failed to overlap, and what you would change.
2. What is the Pallas equivalent of a CUDA thread block, and why is the answer that there isn't one?
3. Read this HLO line aloud, and tell me which memory the output lives in and how many bytes it really occupies.
4. Walk through the design review for LLaMA-3-70B on Ironwood under a 30 ms per-token limit at 32k context.